A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with −250dB FoM
A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with −250dB FoM
复制标题
具有 −250dB FoM 的低于 100MHz 参考驱动 25 至 28GHz 小数 N PLL
DOI:
10.1109/isscc42614.2022.9731628
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发表时间:
2022
期刊:
影响因子:
--
通讯作者:
Weiyu Leng
中科院分区:
文献类型:
--
作者:
Dihang Yang;D. Murphy;H. Darabi;A. Behzad;A. Abidi;S. Au;Sraavan R. Mundlapudi;Kejian Shi;Weiyu Leng
A mm-wave frequency synthesizer with output >25GHz inevitably faces the problems of a large closed-loop gain $f_{\mathsf{VCO}}/f\mathsf{ref}=N$. Phase noise and spurs on the reference input and from other sources in the loop referred to its input are amplified by $N$ A narrow loop bandwidth must be used to limit the resulting jitter. However, now the loop is unable to adequately suppress the oscillator phase noise, leading to a difficult trade-off. At these operating frequencies, the oscillator is inherently noisier since a capacitor bank for digital tuning greatly compromises the overall LC tank quality factor $(Q)$. Therefore, for low output jitter, the synthesizer either needs to allocate disproportionately more current to the VCO than at sub-10GHz, use a sub-10GHz VCO with a frequency multiplier [1], or the reference frequency must be raised to > 100MHz [2], [3], which is beyond the range of reliable, widely available crystal oscillators. In this work, we present a synthesizer that uses a harmonic-mixing (HM) PLL [4], [5] to suppress noise amplification and, therefore, allows the use of a loop with a bandwidth >5MHz. Also, we introduce a coupled mm-wave VCO with only one resonant mode that achieves an FoM (VCO) of 188dB at a 1MHz offset. Combining the two, this synthesizer, driven by a standard 74MHz reference clock, consumes <13mW to deliver 25-to-28GHz output with 88fs rms jitter. It reaches an FoM (PLL) of −250dB.