A hardware wrapper for the SHA-3 hash algorithms
A hardware wrapper for the SHA-3 hash algorithms
复制标题
SHA-3 哈希算法的硬件包装器
DOI：
10.1049/cp.2010.0478
复制
发表时间：
2010
期刊：
影响因子：
--
通讯作者：
Baldwin B
中科院分区：
文献类型：
--
作者：
Baldwin B
第二轮NIST公开竞赛正在进行中，以寻找一种新的散列算法，并将其纳入NIST安全散列标准（SHA-3）。在第二轮比赛中，将讨论硬件算法的计算效率。对于软件实现，NIST为每种设计指定了应用程序编程接口（API）沿着参考实现，从而能够在软件平台上快速轻松地进行比较和测试，但没有为硬件分析提供此类规范。在本文中，我们提出了一个硬件包装接口，试图涵盖所有的竞争项目（实际上，一般的哈希算法）在任何数量的FPGA和ASIC硬件平台。该接口包括通信和填充，并且尝试简化散列算法以允许不同设计之间的准确和公平的面积、定时和功率测量。
The second round of the NIST public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware is to be addressed during the second round of the contest. For software implementations NIST specifies an application programming interface (API) along with reference implementation for each of the designs, thereby enabling quick and easy comparison and testing on software platforms, however no such specification was given for hardware analysis. In this paper we present a hardware wrapper interface which attempts to encompass all the competition entries (and indeed, hash algorithms in general) across any number of both FPGA and ASIC hardware platforms. This interface comprises communications and padding, and attempts to standardise the hashing algorithms to allow accurate and fair area, timing and power measurement between the different designs.