VeGen: a vectorizer generator for SIMD and beyond
VeGen: a vectorizer generator for SIMD and beyond
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DOI：
10.1145/3445814.3446692
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发表时间：
2021-04
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通讯作者：
Yishen Chen;Charith Mendis;Michael Carbin;Saman P. Amarasinghe
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作者：
Yishen Chen;Charith Mendis;Michael Carbin;Saman P. Amarasinghe
矢量指令在现代处理器中无处不在。传统的编译器自动矢量化技术主要针对单指令多数据（SIMD）指令。然而，这些自动矢量化技术还不足以对非simd矢量指令进行建模，而非simd矢量指令可以加速图像处理、数字信号处理和机器学习等领域的应用。为了针对非simd指令，编译器开发人员不得不求助于复杂的、特别的窥视孔优化，这花费了大量的开发时间，同时仍然不足。随着向量指令集的不断快速发展，编译器无法跟上这些新的硬件功能。在本文中，我们引入Lane Level Parallelism (LLP)，它捕获了由SIMD和非SIMD矢量指令实现的并行模型。我们介绍了VeGen，一个矢量生成器，它可以自动生成一个矢量传递，以在仅使用指令语义作为输入的情况下发现程序中特定于目标体系结构的LLP。VeGen解耦，但协调自动生成的目标特定的矢量化实用程序与目标无关的矢量化算法。这种设计使我们能够系统地针对非simd矢量指令，这些指令到目前为止还需要在不同编译器阶段之间进行特别协调。我们证明了VeGen可以有效地使用非simd矢量指令，例如，在x265的idct4内核上获得3倍的加速（与LLVM的矢量器相比）。
Vector instructions are ubiquitous in modern processors. Traditional compiler auto-vectorization techniques have focused on targeting single instruction multiple data (SIMD) instructions. However, these auto-vectorization techniques are not sufficiently powerful to model non-SIMD vector instructions, which can accelerate applications in domains such as image processing, digital signal processing, and machine learning. To target non-SIMD instruction, compiler developers have resorted to complicated, ad hoc peephole optimizations, expending significant development time while still coming up short. As vector instruction sets continue to rapidly evolve, compilers cannot keep up with these new hardware capabilities. In this paper, we introduce Lane Level Parallelism (LLP), which captures the model of parallelism implemented by both SIMD and non-SIMD vector instructions. We present VeGen, a vectorizer generator that automatically generates a vectorization pass to uncover target-architecture-specific LLP in programs while using only instruction semantics as input. VeGen decouples, yet coordinates automatically generated target-specific vectorization utilities with its target-independent vectorization algorithm. This design enables us to systematically target non-SIMD vector instructions that until now require ad hoc coordination between different compiler stages. We show that VeGen can use non-SIMD vector instructions effectively, for example, getting speedup 3× (compared to LLVM’s vectorizer) on x265’s idct4 kernel.