Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors
Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors
复制标题
DOI：
10.1109/vlsi-soc.2018.8644747
复制
发表时间：
2018-10
期刊：
影响因子：
--
通讯作者：
Edouard Giacomin;P. Gaillardon
中科院分区：
文献类型：
--
作者：
Edouard Giacomin;P. Gaillardon
硬件安全漏洞是嵌入式计算设备的主要问题，这些设备现在用于许多应用，如信用卡、SIM卡或金融系统，使敏感数据处于危险之中。这样的系统通常是差分功率攻击的目标，其中可以监视功率跟踪以便访问敏感数据。为了缓解这个问题，文献中提出的一种可能的技术是使用互补门（例如，并行计算XOR和XNOR操作两者），以便对于所有可能的输入组合具有对称的功率迹线。然而，这种技术导致大面积和功率开销，因为它近似地需要两倍数量的晶体管。最近，与互补金属氧化物半导体（CMOS）技术相比，诸如三独立栅极场效应晶体管（TIGFET）的新技术已经被证明能够使用更少的晶体管来实现紧凑的逻辑门。在本文中，我们调查的好处，使用TIGFET的硬件安全性。首先，我们表明，使用互补栅极技术与TIGFET可以减少晶体管的数量，电源线的变化，开关功率和泄漏分别为2倍，57%，36%和8倍，当与CMOS相比。此外，我们表明，对于相同的晶体管数量和类似的开关功率，使用TIGFET可以减少81%和6.7倍的漏电流分别与CMOS相比，功率迹线的变化。
Hardware security vulnerabilities are a major concern for embedded computing devices which are now used in many application such as credit cards, SIM cards, or financial systems, putting sensible data at risk. Such systems are often targeted by differential power attacks, where the power trace can be monitored in order to get access to the sensible data. To alleviate this issue, a possible technique proposed in literature is to use a complementary gate (e.g., computing both XOR and XNOR operations in parallel) in order to have a symmetrical power trace for all possible input combinations. However, this technique results in a large area and power overhead since it approximatively requires twice the number of transistors. Recently, novel technologies such as Three-Independent-Gate Field Effect Transistors (TIGFETs) have been shown to be able to realize compact logic gates using less transistors when compared to Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we investigate the benefits of using TIGFETs in terms of hardware security. First, we show that using the complementary gate technique with TIGFETs can reduce the transistor count, the power trace variation, the switching power and leakage by 2×, 57%, 36% and 8× respectively, when compared to CMOS. In addition, we show that for the same transistor count and similar switching power, using TIGFETs can reduce the power trace variation and the leakage by 81% and 6.7× respectively when compared to CMOS.