Post-fabrication clock-timing adjustment using genetic algorithms
Post-fabrication clock-timing adjustment using genetic algorithms
复制标题
使用遗传算法进行制造后时钟定时调整
DOI：
10.1007/0-387-31238-2_4
复制
发表时间：
2004
影响因子：
5.4
通讯作者：
T. Higuchi
中科院分区：
文献类型：
--
作者：
E. Takahashi;Y. Kasai;M. Murakawa;T. Higuchi
为了解决时钟时序波动的问题（也被称为“时钟偏移”的问题），我们提出了一种方法，利用遗传算法（GA）的制造后时钟时序调整的实施。这种方法是通过专用可调电路和调整软件的结合来实现的，插入时钟线的多个可编程延迟电路的值在制造后由调整软件确定。所提出的方法具有三个优点：（1）提高时钟频率，从而提高操作产量，（2）降低电源电压，同时保持操作产量，以及（3）减少设计时间。两种不同的LSI已经开发出来，第一个是可编程延迟电路，开发的时钟定时调整的一个元素，而第二个是一个中等规模的电路，开发这些优势，在一个真实的芯片。这两个LSI的实验以及设计实验证明了这些优势，时钟频率提高了25%（最大值），电源电压降低了33%，设计时间缩短了21%。此外，我们还提出了一种调整算法，考虑到确保的时序裕度，以科普电源电压和时钟频率的波动。
To solve the problem of fluctuations in clock timing (also known as “clock skew” problems), we propose an approach for the implementation of post-fabrication clock-timing adjustment utilizing genetic algorithms (GA). This approach is realized by the combination of dedicated adjustable circuitry and adjustment software, with the values for multiple programmable delay circuits inserted into the clock lines being determined by the adjustment software after fabrication. The proposed approach has three advantages: (1) enhancement in clock frequencies leading to improved operational yields, (2) lower power supply voltages, while maintaining operational yield, and (3) reductions in design times. Two different LSIs have been developed; the first is a programmable delay circuit, developed as an element of the clock-timing adjustment, while the second is a medium-scale circuit, developed to evaluate these advantages in a real chip. Experiments with these two LSIs, as well as a design experiment, have demonstrated these advantages with an enhancement in clock frequency of 25% (max), a reduction in the power-supply voltage of 33%, and a 21% shorter design time. Furthermore, we also propose an adjustment algorithm that takes into account the ensured timing margins to cope with fluctuations in power supply voltage and clock frequency.