Skewed Multistaged Multibanked Register File for Area and Energy Efficiency
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency
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DOI：
10.1587/transinf.2016edp7414
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发表时间：
2017-04
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影响因子：
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通讯作者：
Junji Yamada;Ushio Jimbo;Ryota Shioya;M. Goshima;S. Sakai
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文献类型：
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作者：
Junji Yamada;Ushio Jimbo;Ryota Shioya;M. Goshima;S. Sakai
包含寄存器文件的区域是高性能内核中的热点，它限制了时钟频率。虽然多组存储极大地减少了超标量处理器核的寄存器堆的面积和能耗，但由于组冲突，它受到低IPC的影响。我们的倾斜多级大大降低了银行冲突的概率，但管道的干扰概率的第二阶段。评估结果表明，与NORCS，这是一个寄存器文件的面积和能源效率的最新研究相比，一个建议的寄存器文件与18个银行实现了39.9%和66.4%的减少电路面积和能源消耗，同时保持相对IPC为97.5%。关键词：超标量处理器、寄存器文件、多银行
The region that includes the register file is a hot spot in high-performance cores that limits the clock frequency. Although multibanking drastically reduces the area and energy consumption of the register files of superscalar processor cores, it suffers from low IPC due to bank conflicts. Our skewed multistaging drastically reduces not the bank conflict probability but the pipeline disturbance probability by the second stage. The evaluation results show that, compared with NORCS, which is the latest research on a register file for area and energy efficiency, a proposed register file with 18 banks achieves a 39.9% and 66.4% reduction in circuit area and in energy consumption, while maintaining a relative IPC of 97.5%. key words: superscalar processor, register file, multibanking