Through Silicon Via technology using tungsten metallization

Through Silicon Via technology using tungsten metallization
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使用钨金属化的硅通孔技术

DOI:
10.1109/icicdt.2011.5783204
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发表时间:
2011
期刊:
2011 IEEE International Conference on IC Design & Technology
影响因子:
--
通讯作者:
N. Sillon
N. Sillon
中科院分区:
--
文献类型:
--
作者:
G. Pares;N. Bresson;S. Minoret;V. Lapras;P. Brianceau;J. Lugand;R. Anciant;N. Sillon

文献摘要

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硅通孔(TSV)是一种非常有前途的先进封装技术,可以替代引线键合。该技术对于SiP、SoP、3D组件集成(例如存储器堆叠)或MEMS结构封装等完全集成的产品来说是必不可少的。目前正在研究不同的替代方案,例如先过孔或后过孔。对于通孔-第一族,可以考虑两种不同的方法。TSV可以在FEOL(预处理方法)之前或在FEOL和BEOL(中间处理方法)之间完成。每个解决方案都有优点和缺点,具体取决于最终应用。在本文的第一部分中,钨中间工艺TSV技术将被介绍,并简要比较铜中间工艺方法。然后,将详细介绍钨TSV的制作过程和形貌特征。我们将重点介绍针对钨TSV技术进行了专门优化的工艺的两个特定部分:低温绝缘氧化物和填充过孔的钨沉积-回蚀序列。将介绍和讨论这些优化的结果。最后,我们将介绍在这项工作中使用的电气测试车,并提出关于过孔电阻的主要结果。在设计和集成规则方面,结合过程约束,提出了一些具体的建议。
Through Silicon Vias (TSV) is a very promising technology in advanced packaging, for the replacement of wire bonding. This technology is becoming mandatory for fully integrated products such as SiP, SoP, 3D components integration (e.g memory stacking), or MEMS structure packaging. Different alternatives are currently investigated such as via-first or via-last. Into the via-first family two different approaches can be considered. The TSV's can be done before the FEOL (pre-process approach) or in-between the FEOL and the BEOL (mid process approach). Each solution has advantages and drawbacks depending on the final application in particular. In a first part of this paper the tungsten mid-process TSV technology will be presented and briefly compared to the copper mid-process approaches. Then, the process of the tungsten TSV fabrication will be detailed and morphological characterizations will be presented. We will focus on two specific parts of the process which have been specifically optimized for the tungsten TSV technology: the low temperature insulation oxide and the tungsten deposition-etch back sequence to fill the vias. The results of those optimizations will be presented and discussed. Last, we will introduce the electrical test vehicle used in this work and present the main results regarding via resistances. Some specific recommendations will by proposed in term of design and integration rules in relation with the process constraints.