Post-verification debugging of hierarchical designs
Post-verification debugging of hierarchical designs
复制标题
分层设计的验证后调试
DOI：
10.1109/iccad.2005.1560184
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
R. Drechsler
中科院分区：
文献类型：
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作者：
M. F. Ali;Sean Safarpour;A. Veneris;M. Abadir;R. Drechsler
随着 VLSI 设计的复杂性和规模不断增加，错误变得更加频繁且难以跟踪。最近的发展已经实现了大部分验证任务的自动化，但调试仍然是一个资源密集型、手动执行的过程。本文弥合了这一差距，因为它开发了强大的自动化调试方法来补充验证过程。与之前的调试技术不同，所提出的技术利用现代设计的分层性质来提高调试的性能和质量。它还根据量化布尔公式可满足性来表述问题，以显着减少内存需求，从而允许调试大型设计。对工业和基准设计进行的大量实验证实了所提出方法的效率和实用性。
As VLSI designs grow in complexity and size, errors become more frequent and difficult to track. Recent developments have automated most of the verification tasks but debugging still remains a resource-intensive, manually conducted procedure. This paper bridges this gap as it develops robust automated debugging methodologies that complement verification processes. Unlike prior debugging techniques, the proposed one exploits the hierarchical nature of modern designs to improve the performance and quality of debugging. It also formulates the problem in terms of Quantified Boolean Formula Satisfiability to obtain dramatic reduction in memory requirements, which allows for debugging of large designs. Extensive experiments conducted on industrial and benchmark designs confirm the efficiency and practicality of the proposed approach.