High-Level Energy Estimation for Submicrometric TSV Arrays
High-Level Energy Estimation for Submicrometric TSV Arrays
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DOI：
10.1109/tvlsi.2017.2713601
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发表时间：
2017-06
影响因子：
2.8
通讯作者：
Lennart Bamberg;Alberto García-Ortiz
中科院分区：
文献类型：
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作者：
Lennart Bamberg;Alberto García-Ortiz
使用硅VIA（TSV）的3D整合是克服当前CMOS技术的互连延迟问题的最有前途的方法之一。抽象但准确的模型，以估计TSV阵列中的模式依赖性能量；这是第一个高级模型金属 - 氧化物 - 血症导向器（MOS）围绕每个TSV的电容和输入信号之间可能的暂时不一致。数据流，一个亚微米9位TSV阵列和65 nm的技术表明，呈现的TSV能量模型的最大误差为5.53％，而最大误差为5.53％传统的高级模型显示出高达79.77％的错误。平面金属电线或编码器复杂性。
The 3-D integration using through silicon vias (TSVs) is one of the most promising approaches to overcome the interconnect delay problem of current CMOS technologies. Nevertheless, the TSV energy consumption is not negligible due to the high capacitive coupling. This paper presents an abstract and yet accurate model to estimate the pattern-dependent energy consumption in arrays of TSVs; it is the first high-level model including the effects of the voltage-dependent metal–oxide–semiconductor (MOS) capacitances surrounding each TSV and a possible temporal misalignment between the input signals. We propose a regression method to estimate the dynamic size of the coupling capacitances as a function of the bit probabilities. Experimental results for real and synthetic data streams, a submicrometer 9-bit TSV array and a 65-nm technology show that the presented TSV energy model exhibits a maximum error of 5.53%, while the traditional high-level model shows errors of up to 79.77%. Furthermore, the new insights provided by our model reveal a possibility to easily boost the efficiency of existing low-power codes for TSV structures by over 10% without affecting the coding efficiency for the planar metal wires or the encoder complexity.