Compact Low-Power Cortical Recording Architecture for Compressive Multichannel Data Acquisition

Compact Low-Power Cortical Recording Architecture for Compressive Multichannel Data Acquisition
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DOI:
10.1109/tbcas.2014.2304582
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发表时间:
2014-12-01
影响因子:
5.1
通讯作者:
Schmid, Alexandre
Schmid, Alexandre
中科院分区:
工程技术2区
文献类型:
--
作者:
Shoaran, Mahsa;Kamal, Mahdad Hosseini;Schmid, Alexandre

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This paper introduces an area- and power-efficient approach for compressive recording of cortical signals used in an implantable system prior to transmission. Recent research on compressive sensing has shown promising results for sub-Nyquist sampling of sparse biological signals. Still, any large-scale implementation of this technique faces critical issues caused by the increased hardware intensity. The cost of implementing compressive sensing in a multichannel system in terms of area usage can be significantly higher than a conventional data acquisition system without compression. To tackle this issue, a new multichannel compressive sensing scheme which exploits the spatial sparsity of the signals recorded from the electrodes of the sensor array is proposed. The analysis shows that using this method, the power efficiency is preserved to a great extent while the area overhead is significantly reduced resulting in an improved power-area product. The proposed circuit architecture is implemented in a UMC 0.18 mu m CMOS technology. Extensive performance analysis and design optimization has been done resulting in a low-noise, compact and power-efficient implementation. The results of simulations and subsequent reconstructions show the possibility of recovering fourfold compressed intracranial EEG signals with an SNR as high as 21.8 dB, while consuming 10.5 mu W of power within an effective area of 250 mu m x 250 mu m per channel.