WBR - word- and block-level hard error repair for memories
WBR - word- and block-level hard error repair for memories
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WBR - 存储器的字级和块级硬错误修复
DOI：
10.1109/nvmts.2013.6632859
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
Patryk Skoncej
中科院分区：
文献类型：
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作者：
Patryk Skoncej
随着特征尺寸的减小，许多现有的半导体存储器面临关于产量、可靠性、可测试性和可制造性的主要问题。为了克服这些问题，正在开发新的存储器技术。固态非易失性存储器是最受关注的，它有望满足即将到来的低成本、低功耗和高性能系统的挑战性需求。然而，尽管它们提供了所有优点，但新兴的非易失性存储器引入了必须解决和解决的挑战。阻止它们更广泛实施的最大障碍之一是可能在生产后或存储器操作期间发生的永久性故障。为了缓解上述问题，发明了一种称为WBR的新型存储器修复方法。它基于分别为每个存储器块用备用数据块替换有缺陷的数据块。WBR中实现的修复程序可以应用于内存字和块级别，提供不同的修复速度和纠正能力。与最近的解决方案（如SAFER和ECP）相比，WBR为小内存字大小提供了更好的内存寿命改善，并为更宽的内存字实现了类似的结果。与最先进的技术相比，WBR可以应用于小至16位的字大小，施加小于12.5%的附加位开销。WBR可以纯粹在硬件中实现，例如以存储器控制器的形式。它是现有的磨损均衡技术的补充，它可以用于最近提出的PAYG框架。
Many existing semiconductor memories face major problems concerning yield, reliability, testability, and manufacturability as the feature size decreases. In order to overcome these issues, new memory technologies are being developed. The greatest attention is paid to solid-state, non-volatile memories which are expected to meet the challenging demands of upcoming low-cost, low-power, and high-performance systems. However, despite all advantages which they offer, emerging non-volatile memories introduce challenges which have to be addressed and solved. One of the biggest obstacles preventing them from wider implementation are permanent faults which can occur right after production or during memory operational time. In order to mitigate the mentioned problem a novel memory repair approach, called WBR, has been invented. It is based on replacing defective data blocks with spare ones for every memory block separately. Repair procedures implemented in the WBR can be applied on memory word- and block-levels offering different repair speeds and correction capabilities. In comparison to recent solutions such as SAFER and ECP, WBR provides better memory lifetime improvement for small memory word sizes and achieves comparable results for wider memory words. In contrast to the state-of-the-art techniques, WBR can be applied to word sizes as small as 16 bits imposing less than 12.5% of additional bit overhead. The WBR can be implemented purely in hardware, e.g. in form of a memory controller. It is complementary to existing wear-leveling techniques, and it can be used in the recently-proposed PAYG framework.