Demonstration of an 8×8-bit RSFQ multi-port register file
Demonstration of an 8×8-bit RSFQ multi-port register file
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8×8位RSFQ多端口寄存器文件演示
DOI：
10.1109/isec.2013.6604257
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
A. K. Kasperek
中科院分区：
文献类型：
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作者：
A. Kirichenko;A. Sahu;T. Filippov;O. Mukhanov;Andriy V. Dotsenko;M. Dorojevets;A. K. Kasperek
作为8位RSFQ处理器数据路径开发的一部分，我们设计、制作并实验演示了一个8×8位RSFQ多端口寄存器文件。寄存器文件提供输入数据操作数并存储算术逻辑单元（ALU）结果。它可以同时执行两个非破坏性的“读”操作和一个“写”操作，并能够存储8个8位字。该设计的显著特点是广泛使用无源传输线（PTL），用于寄存器文件内部非常复杂的互连。该寄存器文件旨在与最近演示的20 GHz 8位RSFQ ALU集成。它是用标准HYPRES的1.0-um 4.5-kA/cm 2工艺制造的。该电路被放置在1 cm × 1 cm的芯片上，由约4，000个约瑟夫森结组成。
As a part of the 8-bit RSFQ processor datapath development, we have designed, fabricated, and experimentally demonstrated an 8×8-bit RSFQ multi-port register file. The register file provides input data operands and stores Arithmetic Logic Unit (ALU) results. It can perform two simultaneous non-destructive “read” operations and one “write” operation and is capable of storing eight 8-bit words. The distinct feature of the design is an extensive use of passive transmission lines (PTLs) for very complex interconnects inside the register file. The register file is designed for integration with recently demonstrated 20-GHz 8-bit RSFQ ALU. It is fabricated with the standard HYPRES's 1.0-um 4.5-kA/cm2 process. The circuit is placed on a 1 cm × 1 cm chip and consists of ~4,000 Josephson junctions.