Virtualizing Hardware with Multi-context Reconfigurable Arrays
Virtualizing Hardware with Multi-context Reconfigurable Arrays
复制标题
使用多上下文可重配置阵列虚拟化硬件
DOI：
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发表时间：
2003
期刊：
影响因子：
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通讯作者：
M. Platzner
中科院分区：
文献类型：
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作者：
Rolf Enzler;Christian Plessl;M. Platzner
与处理器相比，当前的可重构设备完全缺乏允许独立于设备的编译和前向兼容的编程模型。克服这种限制的关键是硬件虚拟化。在本文中，我们采用宏流水线执行模型来实现数据流应用的硬件虚拟化。作为硬件实现，我们提出了一种混合多上下文架构，它将粗粒度可重构阵列附加到主机CPU上。联合仿真框架可以对整个体系结构进行周期精确的仿真。作为一个案例研究，我们将FIR滤波器映射到我们的虚拟化硬件模型并评估不同的设计。我们讨论了上下文的数量和上下文状态的特征对加速和CPU负载的影响。
In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitations is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.