High-Density and Robust STT-MRAM Array Through Device/Circuit/Architecture Interactions
High-Density and Robust STT-MRAM Array Through Device/Circuit/Architecture Interactions
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DOI：
10.1109/tnano.2015.2456510
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发表时间：
2015-07
影响因子：
2.4
通讯作者：
K. Kwon;Xuanyao Fong;Parami Wijesinghe;P. Panda;K. Roy
中科院分区：
文献类型：
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作者：
K. Kwon;Xuanyao Fong;Parami Wijesinghe;P. Panda;K. Roy
在自旋转移扭矩磁随机存取存储器(STT-MRAM)中，保持、写入和读取故障对存储器的成品率和密度有负面影响。在本文中，我们联合考虑器件-电路-体系结构层来实现高密度的STT-MRAM阵列，同时满足目标成品率要求。在设备级考虑不同类型的磁隧道结，并使用纠错码(ECC)和反转编码作为体系结构解决方案。通过跨层交互，我们提出了一种在满足工艺变化下的目标成品率和能耗的同时优化位单元面积的设计方法。此外，为了获得比单独使用ECC获得的更高的存储密度，我们探索了与ECC一起使用反转编码的使用。我们提出的技术可以通过基于两个观察结果适当地选择热稳定因子来进一步提高存储密度：1)反转编码能够以较小的存储开销修复多个读/写故障；2)随着热稳定因子的增加，保留故障概率呈指数下降，因此，简单的ECC足够好地用于保持故障校正。
In spin-transfer torque magnetic random access memory (STT-MRAM), retention-, write-, and read-failures negatively impact the memory yield and density. In this paper, we jointly consider device-circuit-architecture layers to implement high-density STT-MRAM array while meeting the target yield requirement. Different types of magnetic tunnel junctions are considered at the device level, and error correcting codes (ECCs) in conjunction with invert-coding are employed as an architectural solution. Through cross-layer interactions, we present a design methodology to optimize bit-cell area while satisfying the target yield and energy consumption under process variation. Furthermore, we explore the use of invert-coding along with ECC in order to achieve higher memory density than that obtained using ECC alone. Our proposed technique can improve memory density further by proper selection of thermal stability factor based upon two observations: 1) invert-coding can fix multiple write/read failures with small storage overhead and 2) as thermal stability factor increases, retention-failure probability exponentially decreases, and thus, simple ECC is good enough for retention failure correction.