An analog memory integrated circuit for waveform sampling up to 900 MHz
An analog memory integrated circuit for waveform sampling up to 900 MHz
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DOI：
10.1109/23.322884
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发表时间：
1994-08
期刊：
影响因子：
--
通讯作者：
G. Haller;B. Wooley
中科院分区：
文献类型：
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作者：
G. Haller;B. Wooley
介绍了一种适用于高速模拟波形采集的开关电容存储器的设计与实现。所提出的电路的亮点是900 MHz的采样频率（在芯片上产生），输入信号独立的单元的采样和采样实例，以及单元增益是不敏感的元件尺寸。一个双通道版本的存储器与32个单元的每个通道已被集成在一个2-/spl μ/m的互补金属氧化物半导体（CMOS）工艺与多晶硅到多晶硅电容器。在整个输入信号范围内，扣除单元消隐后通道中测得的均方根单元响应变化小于0.3 mV。在2.5 V输入范围内，电池间增益匹配优于0.01% rms，非线性小于0.03%。存储器的动态范围超过13位，在900 MHz采样的21.4 MHz正弦波的峰值信号与（噪声+失真）比为59 dB。>
The design and implementation of a switched-capacitor memory suitable for capturing high-speed analog waveforms is described. Highlights of the presented circuit are a 900 MHz sampling frequency (generated on chip), input signal independent cell pedestals and sampling instances, and cell gains that are insensitive to component sizes. A two-channel version of the memory with 32 cells for each channel has been integrated in a 2-/spl mu/m complementary metal oxide semiconductor (CMOS) process with polysilicon-to-polysilicon capacitors. The measured rms cell response variation in a channel after cell pedestal subtraction is less than 0.3 mV across the full input signal range. The cell-to-cell gain matching is better than 0.01% rms, and the nonlinearity is less than 0.03% for a 2.5-V input range. The dynamic range of the memory exceeds 13 bits, and the peak signal-to-(noise+distortion) ratio for a 21.4 MHz sine wave sampled at 900 MHz is 59 dB. >