A 16–65 cycles/MB H.264/AVC motion compensation architecture for Quad-HD applications
A 16–65 cycles/MB H.264/AVC motion compensation architecture for Quad-HD applications
复制标题
DOI：
--
复制
发表时间：
2011-08
期刊：
影响因子：
--
通讯作者：
Jinjia Zhou;Dajiang Zhou;Gang He;S. Goto
中科院分区：
文献类型：
--
作者：
Jinjia Zhou;Dajiang Zhou;Gang He;S. Goto
提出了一种用于四高清H.264/AVC视频解码器的运动补偿结构。为了满足高吞吐量要求、降低功耗和解决内存延迟问题，本文采用了三种优化方案。首先，提出了一种基于水平-垂直扩展和亮度-色度并行（HVE-LCP）的四分之一像素插值器，有效地将吞吐量提高了至少4倍。其次，采用了一种新颖的缓存存储器组织（4S×4）来提高片上存储器的利用率，有助于节省存储器面积和功耗。最后，拆分任务队列（STQ）架构增强了内存系统的延迟容忍度，从而减少了总体处理时间。该设计的逻辑门计数和片上存储器分别为108.8k和3.1kB。该架构支持在166MHz下3840x 2160@60fps的实时处理。
This paper presents a motion compensation architecture for Quad-HD H.264/AVC video decoder. For meeting the high throughput requirement, reducing power consumption and solving the memory latency problems, three optimization schemes are applied in this work. Firstly, a quarter-pel interpolator based on Horizontal-Vertical Expansion and Luma-Chroma Parallelism (HVE-LCP) is proposed to efficiently increase the throughput by at least 4 times from the previous designs. Secondly, a novel cache memory organization (4S×4) is adopted to improve the on-chip memory utilization, contributing to memory area and power saving. Finally, a Split Task Queue (STQ) architecture enhances the memory system latency tolerance, which reduces overall processing time. This design costs a logic gate count and on-chip memory of 108.8k and 3.1kB, respectively. The proposed architecture supports real-time processing of 3840×2160@60fps at 166MHz.