Protecting analog circuits with parameter biasing obfuscation
Protecting analog circuits with parameter biasing obfuscation
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DOI：
10.1109/latw.2017.7906739
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发表时间：
2017-03
期刊：
影响因子：
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通讯作者：
Vaibhav Venugopal Rao;I. Savidis
中科院分区：
文献类型：
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作者：
Vaibhav Venugopal Rao;I. Savidis
提出了一种通过混淆偏置条件来保护模拟知识产权的方法。以前的研究方法主要集中在保护数字知识产权免受窃取、过度生产、伪造和木马插入。模拟IP没有被研究，因为它不共享用于数字保护的相同复制结构和功能。本文提出的偏置加密技术是在锁相环上实现的。PLL的工作频率使用40位加密密钥在800 MHz到2.2 GHz的范围内进行屏蔽。通过暴力破解确定正确密钥的概率为9.095×10−13。加密锁相环的开销包括有效面积增加6.3%，功耗增加0.89%，相位噪声增加5dBc/Hz。
A methodology to secure analog intellectual property (IP) by obfuscating biasing conditions is presented in this paper. Previous research methodologies have focused on protecting digital IP from theft, overproduction, counterfeiting, and Trojan insertion. Analog IP has not been investigated as it does not share the same replicated structures and functionalities used for digital protection. The bias encryption techniques presented in this paper are implemented on a phase locked loop (PLL). The operating frequency of the PLL is masked in the range of 800 MHz to 2.2 GHz with a 40-bit encryption key. The probability of determining the correct key through brute force attack is 9.095×10−13. The overheads of encrypting the PLL include a 6.3% increase in active area, a 0.89% increase in power consumption, and a 5 dBc/Hz increase in phase noise.