Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 µm SOI-MOSFET
Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 µm SOI-MOSFET
复制标题
埋层工程可减少低于 0.05 µm SOI-MOSFET 的漏极感应势垒降低
DOI：
10.1143/jjap.38.2294
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发表时间：
1999
影响因子：
1.5
通讯作者：
R. Koh
中科院分区：
文献类型：
--
作者：
R. Koh
利用二维器件模拟器研究了埋层结构对绝缘体上硅金属氧化物硅场效应晶体管（SOI MOSFET）漏致势垒降低（DIBL）的影响。埋层厚度和埋层的介电常数系统地变化。研究发现，阈值电压的退化可以分为两个部分。一个分量来自经由SOI层的电通量，另一个分量来自经由掩埋层的电通量。控制埋层厚度和介电常数的埋层绝缘体工程对降低后者是有效的。埋层介电常数为1.0的埋层气隙结构可以使栅长极限减小23%。
The influence of the buried layer structure on the drain-induced barrier lowering (DIBL) is investigated for a silicon-on-insulator metal-oxide-silicon field-effect-transistor (SOI-MOSFET) by a two-dimensional device simulator. The buried layer thickness and the dielectric constant of the buried layer are varied systematically. It is found that the degradation on the threshold voltage can be separated into two components. One component originates from the electric flux via the SOI layer and the other via the buried layer. The buried insulator engineering which controls the thickness and the dielectric constant of the buried layer is effective in reducing the latter component. The gate length limit can be reduced by 23% by the buried air gap structure where the dielectric constant of the buried layer is 1.0.