Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis
Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis
复制标题
自动 CMOS 模拟电路综合的高效性能建模
DOI：
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发表时间：
2021
影响因子：
2.8
通讯作者：
Lihong Zhang
中科院分区：
文献类型：
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作者：
Zhenxin Zhao;Lihong Zhang
快速准确的性能评估可以显著提高模拟电路自动综合的效率。本文提出了一种新的性能建模方法，可以有效地估计电路的性能与建模开销可变的电路拓扑结构。该方法首先利用先进的神经网络（NN）拟合技术进行精确的晶体管建模。然后，它利用建立的晶体管模型和拓扑信息，从电路网表，以精确地发现电路直流工作点。专门的确定性计划已经开发的援助下，从电路网表转换的无向二分图。此外，精确的NN晶体管模型有助于直接导出小信号模型参数值，这些参数值可以进一步用于进行符号分析以评估电路性能。我们的实验结果不仅比较各种确定性直流工作点计算方案，但也证明了高效的模型开发，通用性，快速执行，公平的预测，我们提出的性能建模方法。
Fast and accurate performance estimation can significantly enhance the efficiency of automated analog circuit synthesis. This article presents a novel performance modeling method that can efficiently estimate circuit performance with ignorable model building overhead for variant circuit topologies. The proposed method starts with accurate transistor modeling by taking advantage of the advanced neural network (NN) fitting technique. It then utilizes the established transistor models and topology information from a circuit netlist to precisely discover the circuit dc operating point. Specialized deterministic schemes have been developed with the aid of an undirected bipartite graph converted from the circuit netlist. Moreover, the accurate NN transistor models help directly derive the small-signal model parameter values, which can be further applied to conduct symbolic analysis to evaluate circuit performances. Our experimental results not only compare various deterministic dc operating point computation schemes but also demonstrate the efficient model development, general applicability, speedy execution, and fair prediction of our proposed performance modeling method.