A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS
A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS
复制标题
采用 10nm CMOS 封装、具有 3-Tap FFE 的 112Gb/s PAM-4 发送器
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
F. O’Mahony
中科院分区：
文献类型：
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作者：
Jihwan Kim;A. Balankutty;R. Dokania;A. Elshazly;Hyung Seok Kim;Sandipan Kundu;Skyler Weaver;Kai Yu;F. O’Mahony
对高带宽数据通信基础设施快速增长的需求推动了行业开发符合电气接口标准（如CEI-56G和802.3bs-400GbE）的超高速/密度有线链路。最近的出版物已经展示了CMOS发射机（TX）的工作速度为50-64Gb /s[1-4]，下一代100Gb/s+有线标准的早期规划正在进行中。56Gb/s的长距离有线标准主要采用PAM-4调制方案，该方案与上一代28Gb/s NRZ收发器保持相同的符号速率。然而，对于112Gb/s的收发器，由于信噪比和向后兼容性的权衡，不太可能采用高阶调制（例如PAM-8/16）。因此，112Gb/s PAM-4的符号速率必须比上一代提高一倍，这需要电路带宽和抖动性能提高大约两倍。此外，必须最大限度地提高链路的能源效率，使本地电力输送和系统功耗保持在实际范围内。本文提出了一种可重构的56GS/s三分接FFE TX，在PAM-4下工作速度可达112Gb/s，在NRZ调制下工作速度可达56Gb/s。TX采用四分之一速率架构，基于1 ui脉冲发生器的4:1串行器与CML驱动器相结合，用于pad带宽扩展的多段π线圈，以及每通道占空比检测/校正（DCD/DCC）和正交误差检测/校正（QED/QEC）电路。TX采用10nm FinFET CMOS技术实现，得益于晶体管驱动强度、互连电迁移/电阻和整体面积缩放[5]的改进。
The rapidly growing demand for high-bandwidth data communication infrastructure has fueled the industry to develop ultra-high-speed/density wireline links compliant with electrical interface standards such as CEI-56G and 802.3bs–400GbE. Recent publications have demonstrated CMOS transmitters (TX) operating from 50–64Gb/s [1-4], and early planning for the next generation of 100Gb/s+ wireline standards is underway. Long-reach wireline standards at 56Gb/s have largely adopted a PAM-4 modulation scheme that maintains the same symbol rate as the previous generation of 28Gb/s NRZ transceivers. For 112Gb/s transceivers, however, higher order modulation (e.g., PAM-8/16) is unlikely to be adopted due to the tradeoff in SNR and backward compatibility. Therefore, the symbol rate for 112Gb/s PAM-4 must be doubled relative to the previous generation, which requires circuit bandwidth and jitter performance to improve by roughly a factor of two. In addition, the energy efficiency of the link must be maximized to keep local power delivery and system power consumption within practical limits. This paper presents a reconfigurable 56GS/s 3-tap FFE TX that operates up to 112Gb/s with PAM-4 or at 56Gb/s with NRZ modulation. The TX employs a quarter-rate architecture, a 1-UI pulse-generator-based 4:1 serializer combined with a CML driver, a multi-segment π-coil for pad bandwidth extension, and per-lane duty-cycle detection/correction (DCD/DCC) and quadrature-error detection/correction (QED/QEC) circuits. The TX is implemented in a 10nm FinFET CMOS technology and benefits from improvements to transistor drive strength, interconnect electro-migration/resistance, and overall area scaling [5].