15 nm gate length planar CMOS transistor
15 nm gate length planar CMOS transistor
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15 nm 栅极长度平面 CMOS 晶体管
DOI：
10.1109/iedm.2001.979669
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发表时间：
2001
期刊：
影响因子：
--
通讯作者：
M. Lin
中科院分区：
文献类型：
--
作者：
B. Yu;H. Wang;A. Joshi;Q. Xiang;E. Ibok;M. Lin
将主流平面CMOS晶体管技术继续扩展到深亚100 nm范围越来越具有挑战性，但也是可能的。在本文中，我们报告了体硅平面CMOS晶体管的物理栅极长度缩小到15 nm。在0.8V电源电压下，n沟道FET和p沟道FET的门延迟CV/I分别为0.29ps和0.68ps，能量延迟积分别为42 pJ-ps/m和97 pJ-ps/m。据我们所知，这些数字是迄今为止报道的最佳数字。
Continued scaling of mainstream planar CMOS transistor technology into the deep-sub-100 nm regime is increasingly challenging but possible. In this paper, we report bulk-silicon planar CMOS transistors with the physical gate length scaled down to 15 nm. Gate delays (CV/I) of 0.29 ps for n-channel FET and 0.68 ps for p-channel FET are achieved at a supply voltage of 0.8 V. Energy-delay products are 42 pJ-ps/m for an n-channel FET and 97 pJ-ps/m for a p-channel FET, respectively. To our knowledge; these numbers are the best reported to date.