Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits
Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits
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DOI：
10.1109/date.2009.5090757
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发表时间：
2009-04
期刊：
影响因子：
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通讯作者：
S. Ali;L. Ke;R. Wilcock;P. Wilson
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文献类型：
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作者：
S. Ali;L. Ke;R. Wilcock;P. Wilson
提出了一种新的分层优化方法，它能够优化模拟设计的性能和产量。性能和产量的权衡分析使用多目标进化算法和蒙特卡罗模拟相结合。一个行为模型，结合给定的电路拓扑结构的性能和变化的开发，可用于优化系统级结构。该方法使自上而下的系统优化，不仅为性能，而且为产量。该模型已在Verilog-A中开发，并使用Spectre模拟器进行了广泛的实际设计测试。一个5级压控环形振荡器的性能和变化模型已被开发和PLL设计用于演示在系统级的分层优化。结果已被验证与晶体管级的模拟，并建议一个准确的性能和产量预测可以实现与所提出的算法。
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are analysed using a combination of multi-objective evolutionary algorithms and Monte Carlo simulations. A behavioural model that combines the performance and variation for a given circuit topology is developed which can be used to optimise the system level structure. The approach enables top-down system optimisation, not only for performance but also for yield. The model has been developed in Verilog-A and tested extensively with practical designs using the Spectre simulator. A performance and variation model of a 5 stage voltage controlled ring oscillator has been developed and a PLL design is used to demonstrate hierarchical optimisation at the system level. The results have been verified with transistor level simulations and suggest that an accurate performance and yield prediction can be achieved with the proposed algorithm.