29.3 Non-Magnetic 0.18µm SOI Circulator with Multi-Watt Power Handling Based on Switched-Capacitor Clock Boosting
29.3 Non-Magnetic 0.18µm SOI Circulator with Multi-Watt Power Handling Based on Switched-Capacitor Clock Boosting
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29.3 基于开关电容器时钟升压的具有多瓦功率处理能力的非磁性 0.18μm SOI 循环器
DOI：
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
H. Krishnaswamy
中科院分区：
文献类型：
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作者：
A. Nagulu;Tingjun Chen;G. Zussman;H. Krishnaswamy
最近在基于线性周期时变(LPTV)电路的集成非互易元件的实现方面取得了重大进展[1]、[5]。然而，集成环行器仍然需要在功率处理、时钟功耗、插入损耗(IL)和芯片面积方面实现飞跃，才能与铁氧体环行器或集成互换替代方案(如电平衡双工器(EBD))相比变得引人注目[6]。本文介绍了三项创新--(I)开关电容时钟提升方案，(Ii)基于周期负载电感的高频准分布式T线，以及(Iii)基于开关部分反射T线的回转器--使集成环行器和LPTV电路能够实现这一飞跃。在1 GHz 0.18微米SOI CMOS环行器中展示了这些特性，该环行器具有2.1/2.6dBtx-ANT/ANT-RX IL(比现有技术[4]提高0.3db)、+34dBm Tx-ANT P1db(提高2.5倍或4db)和40%的芯片面积降低，所有这些都在39 mW的功耗下(降低4.4倍)。
There has been significant recent progress in the implementation of integrated non-reciprocal components based on linear periodically-time-varying (LPTV) circuits [1], [5]. Nevertheless, integrated circulators still require a leap forward in power handling, clock power consumption, insertion loss (IL), and chip area to become compelling when compared with ferrite circulators or integrated reciprocal alternatives, such as the electrical-balance duplexer (EBD) [6]. This paper introduces three innovations - (i) a switched-capacitor clock-boosting scheme, (ii) high-Bragg-frequency quasi-distributed T-lines based on periodically loaded inductors, and (iii) a gyrator based on switched partially reflecting T-lines - that enable such a leap for integrated circulators and for LPTV circuits more broadly. These are showcased in a 1GHz 0.18µm SOI CMOS circulator that exhibits 2.1/2.6dB TX-ANT/ANT-RX IL (0.3dB better than prior art [4]), +34dBm TX-ANT P1dB (2.5x or 4dB better), and 40% lower chip area, all at 39mW power consumption (4.4x lower).
DOI：
10.1109/isscc.2017.7870377
发表时间：
2017-02
期刊：
2017 IEEE International Solid-State Circuits Conference (ISSCC)
影响因子：
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作者：
T. Dinc;H. Krishnaswamy
通讯作者：
T. Dinc;H. Krishnaswamy