A 700mV low power low noise implantable neural recording system design.
A 700mV low power low noise implantable neural recording system design.
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700mV低功耗低噪声植入式神经记录系统设计。
DOI：
10.1109/embc.2014.6945130
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发表时间：
2014
期刊：
影响因子：
--
通讯作者：
Rennaker2nd,RobertL
中科院分区：
文献类型：
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作者：
An,Guanglei;Hutchens,Chriswell;Rennaker2nd,RobertL
本文提出了一种用于射频识别 (RFID) 的低功耗、低噪声植入式神经记录接口。该系统中集成了两级神经放大器和 8 位流水线模数转换器 (ADC)。优化的放大器级数展示了最小的功耗和面积消耗；该 ADC 采用新颖的偏移消除技术，对器件漏电具有鲁棒性，可降低输入偏移电压。神经放大器和ADC均采用700mV电源。神经放大器的中频增益为 58.4dB，带宽为 0.71 至 8.26 kHz，带宽为 3dB。测得的输入参考噪声和总功耗分别为 20.7μVrms 和 1.90。该 ADC 在 16Ksps 下实现 8 位精度，输入电压为 ±400mV。综合模拟和测量结果证明了神经记录接口适用于原位中性活动记录。
A low power, low noise implantable neural recording interface for use in a Radio-Frequency Identification (RFID) is presented in this paper. A two stage neural amplifier and 8 bit Pipelined Analog to Digital Converter (ADC) are integrated in this system. The optimized number of amplifier stages demonstrates the minimum power and area consumption; The ADC utilizes a novel offset cancellation technique robust to device leakage to reduce the input offset voltage. The neural amplifier and ADC both utilize 700mV power supply. The midband gain of neural amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7μVrms and 1.90 respectively. The ADC achieves 8 bit accuracy at 16Ksps with an input voltage of ±400mV. Combined simulation and measurement results demonstrate the neural recording interface's suitability for in situ neutral activity recording.