Integrated silicon capacitive accelerometer with PLL servo technique
Integrated silicon capacitive accelerometer with PLL servo technique
复制标题
采用 PLL 伺服技术的集成硅电容式加速度计
DOI：
10.1016/0924-4247(93)80221-2
复制
发表时间：
1993
影响因子：
4.6
通讯作者：
M. Esashi
中科院分区：
文献类型：
--
作者：
Y. Matsumoto;M. Esashi
采用 CMOS 和微加工技术开发了集成硅电容式加速度计。加速度计芯片具有玻璃-硅-玻璃结构，尺寸为3.7 × 4.5 × 0.9 mm3in。硅地震质量块由完全对称的氮氧化硅梁悬挂。传感器电容形成在硅块和上玻璃上的金属电极之间。硅芯片上集成了 CMOS 电容频率 (C–F) 转换器。该电路设计为对温度和电源电压稳定。该电路中有一个参考电容，电路的漂移是通过电路连接到参考电容时获得的信息来补偿的。加速度计芯片的输出频率随加速度线性变化。使用加速度计芯片和外部锁相环（PLL）伺服电路实现了力平衡系统。输出电压随加速度线性变化，输出电压的灵敏度和偏置可以通过外部电路参数调节。
An integrated silicon capacitive accelerometer has been developed with CMOS and micromachining technology. The accelerometer chip has glass—silicon—glass structure and is 3.7 × 4.5 × 0.9 mm3in size. A silicon seismic mass is suspended with silicon-oxinitride beams in full symmetry. The sensor capacitance is formed between the silicon mass and a metal electrode on the upper glass. A CMOS capacitance to frequency (C–F) converter is integrated on the silicon chip. The circuit is designed to be stable to temperature and supply voltage. The circuit has a reference capacitor in it, and the drift of the circuit is compensated by the information obtained when the circuit is connected to the reference capacitor. The output frequency of the accelerometer chip varies linearly with acceleration. The force-balancing system has been realized using the accelerometer chip and an outer phase-locked-loop (PLL) servo circuit. The output voltage varies linearly with acceleration, and the sensitivity and offset of the output voltage can be adjusted with the outer circuit parameter.