Thousands of conductance levels in memristors integrated on CMOS
Thousands of conductance levels in memristors integrated on CMOS
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DOI：
10.1038/s41586-023-05759-5
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发表时间：
2023-03-30
期刊：
影响因子：
64.8
通讯作者：
Yang, J. Joshua
中科院分区：
文献类型：
--
作者：
Rao, Mingyi;Tang, Hao;Yang, J. Joshua
基于忆阻器件（1-3）的神经网络能够提高机器学习（4,5）和人工智能(6)的吞吐量和能源效率，特别是在边缘应用（7-21）中。因为从头开始训练一个神经网络模型在硬件资源、时间和精力方面都是昂贵的，所以在分布在边缘的数十亿个记忆神经网络上单独进行训练是不切实际的。一种实用的方法是下载从云训练中获得的突触权重，并将其直接编程到忆阻器中，以实现边缘应用的商业化。可以在应用后或应用过程中对忆阻电导进行一些后调，以适应特定的情况。因此，在神经网络应用中，忆阻器需要高精度的可编程性，以保证在大量忆阻网络中具有一致和准确的性能（22-28）。这需要在每个记忆器件上有许多可区分的电导水平，不仅是实验室制造的器件，而且在工厂制造的器件。具有许多电导状态的模拟忆阻器也有利于其他应用，例如神经网络训练，科学计算甚至“人类计算”（25,29,30）。在这里，我们报告了在一个商业铸造厂的互补金属氧化物半导体（CMOS）电路上单片集成256 x 256忆阻器阵列的全集成芯片中，用忆阻器实现了2,048个电导水平。我们已经确定了以前限制在忆阻器中可以实现的电导水平数量的潜在物理，并开发了电气操作协议来避免这种限制。这些结果提供了对忆阻开关微观图像的基本理解，以及为各种应用实现高精度忆阻器的方法。
Neural networks based on memristive devices(1-3) have the ability to improve throughput and energy efficiency for machine learning(4,5) and artificial intelligence(6), especially in edge applications(7-21). Because training a neural network model from scratch is costly in terms of hardware resources, time and energy, it is impractical to do it individually on billions of memristive neural networks distributed at the edge. A practical approach would be to download the synaptic weights obtained from the cloud training and program them directly into memristors for the commercialization of edge applications. Some post-tuning in memristor conductance could be done afterwards or during applications to adapt to specific situations. Therefore, in neural network applications, memristors require high-precision programmability to guarantee uniform and accurate performance across a large number of memristive networks(22-28). This requires many distinguishable conductance levels on each memristive device, not only laboratory-made devices but also devices fabricated in factories. Analog memristors with many conductance states also benefit other applications, such as neural network training, scientific computing and even `mortal computing'(25,29,30.) Here we report 2,048 conductance levels achieved with memristors in fully integrated chips with 256 x 256 memristor arrays monolithically integrated on complementary metal-oxide-semiconductor (CMOS) circuits in a commercial foundry. We have identified the underlying physics that previously limited the number of conductance levels that could be achieved in memristors and developed electrical operation protocols to avoid such limitations. These results provide insights into the fundamental understanding of the microscopic picture of memristive switching as well as approaches to enable high-precision memristors for various applications.