Using FPGAs to Accelerate Myers Bit-Vector Algorithm
Using FPGAs to Accelerate Myers Bit-Vector Algorithm
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使用 FPGA 加速 Myers 位向量算法
DOI：
10.1007/978-3-319-32703-7_104
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
M. Bogdan
中科院分区：
文献类型：
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作者：
Jörn Hoffmann;Dirk Zeckzer;M. Bogdan
提出了一种基于概念验证的Myers位向量近似字符串匹配算法的硬件实现。在位向量运算方面，利用现场可编程门阵列(现场可编程门阵列)的大规模并行计算能力来加速算法。该系统在嵌入式平台上实现，具有较高的计算效率和能效。与运行在嵌入式处理器上最快的软件实现相比，仅考虑计算，硬件实现的总体加速约为2%，加速约为8%。
We present a proof-of-concept implementation of Myers bit-vector algorithm for approximate string matching in hardware. In terms of bit-vector operations, the algorithm is accelerated by using the massive parallel computing capabilities of a field programmable gate array (FPGA). The system is realized on an embedded platform with a high computational and energy efficiency. Compared to the fastest software implementation running on the embedded processor, the hardware achieves an overall speed-up of approximately 2 and a speed-up of approximately 8 considering the computation only.