FPGA-based deep-pipelined architecture for FDTD acceleration using OpenCL
FPGA-based deep-pipelined architecture for FDTD acceleration using OpenCL
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DOI：
10.1109/icis.2016.7550742
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发表时间：
2016-08
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通讯作者：
Hasitha Muthumala Waidyasooriya;M. Hariyama
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文献类型：
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作者：
Hasitha Muthumala Waidyasooriya;M. Hariyama
FDTD（有限差分时间域）计算的加速度对于电磁模拟非常重要。使用多核CPU和CPU的常规FDTD加速度方法由于大量并行数据访问而具有记忆带宽限制的常见问题。尽管FPGA有可能解决此问题，但是成功实施架构需要很长的设计，测试和调试时间。为了解决此问题，我们建议使用称为OpenCL（开放计算语言）的类似C的编程语言设计的FPGA架构。因此，设计时间非常小，并且不需要关于硬件设计的广泛知识。我们在FPGA上实施了拟议的体系结构，并实现了超过114个处理能力。与CPU和GPU实施相比，我们还取得了超过13倍和4倍的速度。
Acceleration of the FDTD (finite-difference time-domain) computation is very important for the electromagnetic simulations. Conventional FDTD acceleration methods using multicore CPUs and CPUs have the common problem of memory-bandwidth limitation due to a large amount of parallel data access. Although FPGAs have the potential to solve this problem, very long design, testing and debugging time is required to implement an architecture successfully. To solve this problem, we propose an FPGA architecture designed using C-like programming language called OpenCL (open computing language). Therefore, the design time is very small and extensive knowledge about hardware-design is not required. We implemented the proposed architecture on an FPGA and achieved over 114 GFLOPS of processing power. We also achieved more than 13 times and 4 times speed-up compared to CPU and GPU implementations respectively.