A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components : (Invited Paper)
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components : (Invited Paper)
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使用开源硬件组件进行敏捷芯片开发的可扩展方法：（特邀论文）
DOI：
10.1145/3508352.3561102
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发表时间：
2022
期刊：
影响因子：
--
通讯作者：
P. Bose
中科院分区：
文献类型：
--
作者：
Maico Cassel dos Santos;Tianyu Jia;M. Cochet;Karthik Swaminathan;Joseph Zuckerman;Paolo Mantovani;Davide Giri;J. Zhang;Erik Jens Loscalzo;Gabriele Tombesi;Kevin Tien;Nandhini Chandramoorthy;J. Wellman;David Brooks;Gu;K. Shepard;L. Carloni;P. Bose
我们提出了一种可扩展的方法，用于基于区块的异构片上系统（SoC）架构的敏捷物理设计，简化了开源硬件组件的重用和集成。该方法利用了基于多平面片上网络 (NoC) 的片上通信基础设施的规律性以及将区块连接到 NoC 的套接字接口的模块化。每个插座还为其块提供一组平台服务，包括独立的时钟和电压控制。因此，每个区块的物理设计可以与其在 SoC 顶层布局规划中的位置解耦，并且整体 SoC 设计可以受益于分层时序收敛流程、设计重用以及（如果需要）快速重新设计。通过所提出的方法，我们完成了两次复杂性不断增加的 SoC 流片，这说明了其功能以及由此带来的设计生产力提升。
We present a scalable methodology for the agile physical design of tile-based heterogeneous system-on-chip (SoC) architectures that simplifies the reuse and integration of open-source hardware components. The methodology leverages the regularity of the on-chip communication infrastructure, which is based on a multi-plane network-on-chip (NoC), and the modularity of socket interfaces, which connect the tiles to the NoC. Each socket also provides its tile with a set of platform services, including independent clocking and voltage control. As a result, the physical design of each tile can be decoupled from its location in the top-level floorplan of the SoC and the overall SoC design can benefit from a hierarchical timing-closure flow, design reuse and, if necessary, fast respin. With the proposed methodology we completed two SoC tapeouts of increasing complexity, which illustrate its capabilities and the resulting gains in terms of design productivity.