Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation
复制标题
使用串联门控差分对电路的细粒度多值可重构VLSI及其评估
DOI：
10.1093/ietele/e91-c.9.1437
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
M. Kameyama
中科院分区：
文献类型：
--
作者：
N. Okada;M. Kameyama
一个细粒度可重构VLSI的各种应用，包括算术运算的开发。在细粒度架构中，重要的是定义导致逻辑块的高利用率和开关块的减少的单元功能。从这个角度出发，提出了一种适合于位串行可重构计算的基于泛文字的多值单元。采用串联选通差分对电路，有效地实现了和的全加器电路和通用文字电路。因此，可以使用电路技术构造简单的逻辑块。此外，通过利用多值信令可以降低互连复杂度，其中引入了串行数据比特和指示一个字的标题的开始信号的叠加。差分对电路也被有效地用于电流输出复制，这导致高速信号到相邻的单元。评估是基于90 nm CMOS设计规则，它是明确的，提出的单元的面积可以减少到78%，相比的CMOS implatiuon。此外，其面积时间积为92%，而延迟时间增加了18%。
A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit-serial reconfigurable computation is proposed. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a simple logic block can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple-valued signaling, where superposition of serial data bits and a start signal which indicates heading of one-word is introduced. Differential-pair circuits are also effectively employed for current-output replication, which leads to high-speed signaling to adjacent cells The evaluation is done based on 90 nm CMOS design rule, and it is made clear that the area of the proposed cell can be reduced to 78% in comparison with that of the CMOS implementatiuon. Moreover, its area-time product becomes 92% while the delay time is increased by 18%.