Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds
Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds
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偏置投票：一种在存在可变门逻辑阈值的情况下模拟 CMOS 桥接故障的方法
DOI：
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发表时间：
1993
期刊：
影响因子：
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通讯作者：
R. Aitken
中科院分区：
文献类型：
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作者：
P. Maxwell;R. Aitken
为了正确地模拟桥接故障的影响，有必要考虑到并非所有门的输入都具有相同的逻辑阈值。本文提出了一种通用技术，该技术可用于确定晶体管的特定结构是否会产生高于或低于给定阈值的桥电压，在大多数情况下无需电路模拟。如果需要，该技术还可以用于预测实际电压，这与SPICE模拟非常吻合。该方法在准确模拟桥接故障方面比以前的方法要快得多
In order to simulate the effects of bridging faults correctly it is necessary to take into account the fact that not all gate inputs have the same logic threshold. This paper presents a general technique which can be used to determine if a particular structure of transistors gives rise to a bridge voltage which is higher or lower than a given threshold, in most cases without requiring circuit simulation. If desired, the technique can also be used to predict actual voltages, which agree well with SPICE simulations. The approach is substantially faster than previous approaches for accurately simulating bridging faults.<<ETX>>