Perfect Column-Layered Two-Bit Message-Passing LDPC Decoder and Architectures
Perfect Column-Layered Two-Bit Message-Passing LDPC Decoder and Architectures
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完美的列分层两位消息传递 LDPC 解码器和架构
DOI：
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发表时间：
2018
期刊：
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通讯作者：
Alex Bazarsky
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文献类型：
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作者：
Xinmiao Zhang;Alex Bazarsky
闪存和其他存储器可以采用多级低密度奇偶校验（LDPC）解码器来降低平均解码延迟和功耗。为了满足下一代数据中心越来越严格的延迟限制，早期解码器需要具有更好的纠错能力和更低的延迟。为了实现这一目标，本文首先开发了一种列分层调度方案的2位消息传递（TBMP）LDPC解码算法，这具有显着的编码增益比3位最小和算法。所提出的列分层方案是完美的，在这个意义上，它不会导致任何编码增益退化。同时，利用2位特性，设计了列分层和非分层TBMP算法的有效VLSI结构。复杂度分析表明，对于示例（17664，16560）LDPC码，与行分层的3比特最小和解码器相比，分层（非分层）TBMP解码器以53%（8%）的更大面积为代价具有超过10（8）倍的更短延迟。
Flash and other memories may adopt multi-stage low-density parity-check (LDPC) decoders to reduce the average decoding latency and power consumption. To meet the increasingly tighter latency constraints of next-generation data centers, the earlier-stage decoders need to have better error-correcting capability and lower latency. To achieve this goal, this paper first develops a column-layered scheduling scheme for the 2-bit message-passing (TBMP) LDPC decoding algorithm, which has significant coding gain over the 3-bit Min-sum algorithm. The proposed column-layered scheme is perfect in the sense that it does not cause any coding gain degradation. Also by utilizing the 2-bit property, efficient VLSI architectures are designed for the column-layered and non-layered TBMP algorithms. Complexity analysis shows that, the layered (non-layered) TBMP decoder has more than 10 (8) times shorter latency at the cost of 53% (8%) larger area compared to a row-layered 3-bit Min-sum decoder for an example (17664, 16560) LDPC code.