Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing
Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing
复制标题
用于加速并行处理的可重构硬件的空间和时间共享
DOI：
10.1007/978-3-642-12133-3_21
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
T. El
中科院分区：
文献类型：
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作者：
E. El;Vikram K. Narayana;T. El
高性能可重构计算机（HPRC）是由FPGA和微处理器组成的并行机，FPGA用作协处理器。这种系统上的并行应用程序的执行主要遵循单程序多数据（SPMD）模型，然而，由于可重构（协）处理器相对于（主）处理器的不对称分布，整体系统资源往往未得到充分利用。此外，随着包含多/众核技术的HPRC的引入，系统资源的未充分利用变得更加明显，特别是对于多任务和多用户使用。为了解决不对称问题，我们提出了一种基于部分运行时重配置（PRTR）的资源虚拟化解决方案。所提出的技术允许（主）处理器之间的可重配置（协）处理器的空间、时间和/或空间-时间共享，从而增加了整个系统的利用率。我们通过在Cray XD 1平台上的实验实现验证了随机执行模型的有效性。结果证明了良好的性能和可扩展性特征。
High-Performance Reconfigurable Computers (HPRCs) are parallel machines consisting of FPGAs and microprocessors, with the FPGAs used as co-processors. The execution of parallel applications on such systems has mainly followed the Single-Program Multiple-Data (SPMD) model; however, overall system resources are often underutilized because of the asymmetric distribution of the reconfigurable (co-)processors relative to the (main) processors. Furthermore, with the introduction of HPRCs containing multi/many-core technologies, underutilization of system resources becomes more obvious especially for multi-tasking and multi-user usage. To address the asymmetry problem, we propose a resource virtualization solution based on Partial Run-Time Reconfiguration (PRTR). The proposed technique allows space, time, and/or space-time sharing of the reconfigurable (co-)processors among the (main) processors and thus increasing the overall system utilization. We show the effectiveness of the proposed concepts through a stochastic execution model verified with experimental implementations on the Cray XD1 platform. The results demonstrate favorable performance as well as scalability characteristics.