All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
复制标题
用于充电泵锁相环的全数字内置自测试方案
DOI：
10.1049/cds2.12000
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
Jifei Tang
中科院分区：
文献类型：
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作者：
Lanhua Xia;Jifei Tang
电荷泵锁相环（CP-PLL）广泛用于在片上系统（SoC）中生成定时信号。然而，SoC中嵌入的内核数量、有限的I/O端口资源以及外部测试设备的成本导致测试复杂度和成本的增加。提出了一种 CP-PLL 的全数字内置自测试结构，特别适合 I/O 端口资源有限时的低成本生产测试。该结构简单，只需几个 DFF、MUX 和被测 CP-PLL 中的一些现有电路即可轻松实现。它减少了对额外外部测试时钟和高性能测试设备的需求，从而降低了整个集成电路的测试成本。结合所提出的校准技术，消除了压控振荡器输入电压的不确定初始值对故障覆盖率的影响。因此，测试结果的可靠性也增加了。实验结果证明了该方案的有效性，故障覆盖率高达99.16%。此外，物理芯片设计显示出 1.37% 的低面积开销。
Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital built‐in self‐test structure of CP‐PLL especially suitable for low‐cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP‐PLL under test. It reduces the requirement of additional external test clocks and high‐performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%.