Layout Design Flow for RSFQ Circuits Based on Cell Clustering and Mixed Wiring of JTLs and PTLs
Layout Design Flow for RSFQ Circuits Based on Cell Clustering and Mixed Wiring of JTLs and PTLs
复制标题
基于单元聚类和JTL与PTL混合布线的RSFQ电路版图设计流程
DOI：
10.1109/tasc.2020.3014928
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发表时间：
2020
影响因子：
1.8
通讯作者：
and Naofumi Takagi
中科院分区：
文献类型：
--
作者：
Takashi Dejima;Kazuyoshi Takagi;and Naofumi Takagi
本文提出了一种快速单通量量子电路的自动布局设计流程。为了实现小电路面积和低时延，互连采用约瑟夫森传输线（JTLs）和无源传输线（PTLs）。考虑到jtl和ptl的有效使用，执行放置和路由。逻辑单元被分组到集群中，jtl在集群中使用。物理带库用于集群之间。放置过程由三个步骤组成：第一步，单元聚类；第二步，单元在每个集群中放置和JTL路由；第三步，集群放置。在放置过程之后，集群之间的路由使用物理带库执行。我们将提出的设计流程应用于具有数百个栅极的采样电路。虽然电路面积没有得到充分优化，但采用该设计流程设计的电路的延迟比手工设计的电路低。
An automated layout design flow for rapid single-flux-quantum circuits is proposed in this article. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering effective use of JTLs and PTLs. Logic cells are grouped into clusters, and JTLs are used inside clusters. PTLs are used among clusters. The placement process is composed of three steps: first, cell clustering, second, cell placement and JTL routing in each cluster, and third, cluster placement. After the placement process, routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed by the proposed design flow are lower than those of the circuits designed manually.