A 41.2 nJ/class, 32-Channel On-Chip Classifier for Epileptic Seizure Detection
A 41.2 nJ/class, 32-Channel On-Chip Classifier for Epileptic Seizure Detection
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用于癫痫发作检测的 41.2 nJ/class、32 通道片上分类器
DOI：
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发表时间：
2018
期刊：
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通讯作者：
A. Emami
中科院分区：
文献类型：
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作者：
Milad Taghavi;B. Haghi;Masoud Farivar;Mahsa Shoaran;A. Emami
提出了一种用于癫痫发作检测的41.2 nJ/类、32通道、患者特定的片上分类架构。所提出的片上系统（SoC）通过采用面积和存储器高效技术打破了严格的能量-面积-延迟权衡。八个梯度提升决策树的集合，每个都有一个完全可编程的特征提取引擎（FEE）和FIR滤波器，连续处理输入通道。在闭环体系结构中，FEE重用单个过滤器结构来执行决策树的自顶向下流。FIR滤波器系数从共享存储器复用。采用TSMC 65 nmCMOS工艺制作了540 × 1850 μm2的1 kB寄存器型存储器原型。所提出的片上分类器在来自20名患者（包括361次癫痫发作）的2253小时颅内EEG（iEEG）数据上进行了验证，特异性为88.1%，灵敏度为83.7%。与现有分类器相比，该分类器在能量-面积延迟乘积上提高了27倍。
A 41.2 nJ/class, 32-channel, patient-specific onchip classification architecture for epileptic seizure detection is presented. The proposed system-on-chip (SoC) breaks the strict energy-area-delay trade-off by employing area and memoryefficient techniques. An ensemble of eight gradient-boosted decision trees, each with a fully programmable Feature Extraction Engine (FEE) and FIR filters are continuously processing the input channels. In a closed-loop architecture, the FEE reuses a single filter structure to execute the top-down flow of the decision tree. FIR filter coefficients are multiplexed from a shared memory. The 540 × 1850 μm2 prototype with a 1kB register-type memory is fabricated in a TSMC 65nm CMOS process. The proposed on-chip classifier is verified on 2253 hours of intracranial EEG (iEEG) data from 20 patients including 361 seizures, and achieves specificity of 88.1% and sensitivity of 83.7%. Compared to the state-of-the-art, the proposed classifier achieves 27 × improvement in Energy-AreaLatency product.