A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology
A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology
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采用 65 nm CMOS 技术的 0.56 THz 锁相频率合成器
DOI：
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发表时间：
2016
影响因子：
5.4
通讯作者：
Mau
中科院分区：
文献类型：
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作者：
Yan Zhao;Zuow;Yuan Du;Yilei Li;R. Hadi;G. Virbila;Yinuo Xu;Yanghyo Kim;A. Tang;T. Reck;Mau
本文介绍了一个0.56太赫兹频率合成器的设计和性能的标准65 nm CMOS工艺实现。它的前端由三重推考毕兹振荡器（TPCO），其次是第一和第二级注入锁定分频器（ILFD）和16分频链。TPCO用于将其基频增加三倍至0.53-0.56 THz，而ILFD和随后的分频器链用于将这些频率分频至2.7-2.9 GHz。其后端由独立的频率和相位锁定环路组成，采用独特的CMOS电路设计来实现所需的频率/相位锁定，包括：1）频带选择电感开关; 2）TPCO和第一ILFD上的同时体电压调谐;以及3）第一ILFD的双端口注入架构。该样机实现了21 GHz的频率锁定，在1 MHz偏移处相位噪声低于-74 dBc/Hz，直流功耗为174 mW。
This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53-0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7-2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than -74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.
辐射功率高达 1 mW 的 0 53 THz 可重构光源模块，适用于太赫兹成像应用中的漫射照明
影响因子：
5.4
作者：
U. R. Pfeiffer;Y. Zhao;J. Grzyb;R. Al Hadi;N.Sarmah;Neelanjan;W. Föster;H. Rücker;B. Heinemann
通讯作者：
B. Heinemann