Superconducting Computing with Alternating Logic Elements
Superconducting Computing with Alternating Logic Elements
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DOI：
10.1109/isca52012.2021.00057
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发表时间：
2021-06
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影响因子：
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通讯作者：
Georgios Tzimpragos;Jennifer Volk;A. Wynn;James E. Smith;T. Sherwood
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作者：
Georgios Tzimpragos;Jennifer Volk;A. Wynn;James E. Smith;T. Sherwood
尽管超导单通量量子（SFQ）技术提供了低延迟操作的潜力，每个门的能量耗散为阿焦耳数量级，但其固有的脉冲驱动性质和状态单元导致了每个逻辑门都被时钟化的设计。这意味着必须添加时钟缓冲器来平衡逻辑路径长度，并且每个门都成为一个管道级。我们提出了一种不同的方法，其中门是无时钟的，同步设计具有传统的外观和感觉。尽管没有时钟，但是门本质上是状态机。为了正确地管理这些状态机，逻辑时钟周期由两个同步交替的阶段组成：第一个阶段实现所需的功能，第二个阶段将状态机返回到基态。此外，为了解决与基于脉冲的系统中布尔NOT操作的异步实现相关的挑战，值被表示为无序二进制代码-特别是双轨代码。对于无序代码，AND和OR操作在功能上是完整的。我们证明了我们的新方法xSFQ，其双轨结构和交替时钟相位，以及“双泵浦”逻辑锁存器和通过锁存器分解进行的定时优化，能够实现任意数字设计，而无需门级流水线和附带的开销。我们通过详细的模拟电路建模、脉冲级离散事件仿真和高级管道效率分析来评估这种方法所实现的能量延迟权衡。结果表明，即使在管道危险比（HR）低于1%的情况下，该系统也比传统的SFQ系统提供了能量延迟积（EDP）增益。当风险比分别为15%和20%，设计类似于RISC-V RV32I内核（不包括联锁逻辑的成本）时，xSFQ可以分别节省22x和31x的EDP。
Although superconducting single flux quantum (SFQ) technologies offer the potential for low-latency operation with energy dissipation of the order of attojoules per gate, their inherently pulse-driven nature and stateful cells have led to designs in which every logic gate is clocked. This means that clocked buffers must be added to equalize logic path lengths, and every gate becomes a pipeline stage. We propose a different approach, where gates are clock-free and synchronous designs have a conventional look-and-feel. Despite being clock-free, however, the gates are state machines by nature. To properly manage these state machines, the logical clock cycle is composed of two synchronous alternating phases: the first of which implements the desired function, and the second of which returns the state machines to the ground state. Moreover, to address the challenges associated with the asynchronous implementation of Boolean NOT operations in pulse-based systems, values are represented as unordered binary codes – in particular, dual-rail codes. With unordered codes, AND and OR operations are functionally complete.We demonstrate that our new approach, xSFQ, with its dual-rail construction and alternating clock phases, along with "double-pumped" logical latches and a timing optimization through latch decomposition, is capable of implementing arbitrary digital designs without gate-level pipelining and the overheads that come with it. We evaluate energy-delay trade-offs enabled by this approach through a mix of detailed analog circuit modeling, pulse-level discrete-event simulation, and high-level pipeline efficiency analysis. The resulting systems are shown to deliver energy-delay product (EDP) gains over conventional SFQ even with pipeline hazard ratios (HR) below 1%. For hazard ratios equal to 15% and 20% and a design resembling a RISC-V RV32I core (excluding the cost of interlock logic), xSFQ achieves 22x and 31x EDP savings, respectively.