Research Challenges for On-Chip Interconnection Networks

Research Challenges for On-Chip Interconnection Networks
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DOI:
10.1109/mm.2007.91
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发表时间:
2007-09
期刊:
影响因子:
3.6
通讯作者:
John Douglas Owens;W. Dally;R. Ho;D. Jayasimha;S. Keckler;L. Peh
John Douglas Owens;W. Dally;R. Ho;D. Jayasimha;S. Keckler;L. Peh
中科院分区:
计算机科学3区
文献类型:
--
作者:
John Douglas Owens;W. Dally;R. Ho;D. Jayasimha;S. Keckler;L. Peh

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片上互连网络正迅速成为消费级嵌入式系统中常见的商品多核处理器和SoC的关键使能技术,美国国家科学基金会发起了一个研讨会,讨论OCIN技术、设计和实现方面即将到来的研究问题,并为该领域的研究人员设定了方向。
On-chip interconnection networks are rapidly becoming a key enabling technology for commodity multicore processors and SoCs common in consumer embedded systems, the National Science Foundation initiated a workshop that addressed upcoming research issues in OCIN technology, design, and implementation and set a direction for researchers in the field.