How to Maximize the Potential of FPGA Resources for Modular Exponentiation
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
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如何最大限度地发挥 FPGA 资源的模幂潜力
DOI：
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发表时间：
2007
期刊：
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通讯作者：
D. Suzuki
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文献类型：
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作者：
D. Suzuki
本文介绍了一种模块化的凸起处理方法和电路架构，该方法可以表现出FPGA资源的最大性能。美国提出的模块化凸起体系结构包括三种主要技术。第一种技术是改善蒙哥马利乘法算法，以最大程度地提高FPGA中乘法单元的性能。第二种技术是改善和平衡电路延迟。第三种技术是确保并快速实现有效FPGA资源的可扩展性。我们提出了一个可以使用相同电路来处理多个数据长度的电路体系结构。此外，我们的体系结构可以使用小规模资源进行快速操作。特别是，它可以通过XC4VF12-10SF363在0.26毫秒内完成512位模块化启动，这是VirTex-4系列FPGAS中的最小逻辑资源。另外，使用的切片数量约为。 4000以进行非常紧凑的设计。此外，可以在同一电路中处理1024-，1536和2048-BIT模块化指示。
This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation architecture proposed by us comprises three main techniques. The first technique is to improve the Montgomery multiplication algorithm in order to maximize the performance of the multiplication unit in FPGA. The second technique is to improve and balance the circuit delay. The third technique is to ensure and make fast the scalability of the effective FPGA resource. We propose a circuit architecture that can handle multiple data lengths using the same circuits. In addition, our architecture can perform fast operations using small-scale resources; in particular, it can complete 512-bit modular exponentiation in 0.26 ms by means of XC4VF12-10SF363, which is the minimum logic resources in the Virtex-4 Series FPGAs. Also, the number of SLICEs used is approx. 4000 to make a very compact design. Moreover, 1024-, 1536- and 2048-bit modular exponentiations can be processed in the same circuit with the scalability.