Space and time compaction schemes for embedded cores
Space and time compaction schemes for embedded cores
复制标题
嵌入式内核的空间和时间压缩方案
DOI：
10.1109/test.2001.966670
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发表时间：
2001
期刊：
影响因子：
--
通讯作者：
A. Orailoglu
中科院分区：
文献类型：
--
作者：
O. Sinanoglu;A. Orailoglu
在片上系统中测试嵌入式核心需要使用的测试访问机制，它提供了芯片和核心I/O之间的测试数据的运输。我们概述了一个无混叠的空间和时间压缩方案，组合和顺序的核心，最大限度地减少所需的测试带宽，并降低了测试访问机制在核心输出侧的带宽消耗。实验结果表明，在不增加测试时间的情况下，实现了测试带宽增益。
Testing embedded cores in a system-on-a-chip necessitates the use of a test access mechanism, which provides for transportation of the test data between the chip and the core I/Os. We outline an aliasing-free space and time compaction scheme, for both combinational and sequential cores, which minimizes the required test bandwidth and reduces the bandwidth consumption of the test access mechanism at the core output side. The experimental results show that the test bandwidth gain is achieved with no appreciable increase in test application time.