Leakage Current Reduction in Data Caches on Embedded Systems
Leakage Current Reduction in Data Caches on Embedded Systems
复制标题
嵌入式系统数据缓存中漏电流的减少
DOI：
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
P. López
中科院分区：
文献类型：
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作者：
R. Ubal;J. Sahuquillo;S. Petit;H. Hassan;P. López
如今，嵌入式系统可以在多种普遍的设备（例如智能手机，PDA或视频/数码相机）中找到。这些设备包含较大的缓存记忆，其功耗可能达到总支出能量的50％，从中，泄漏能量是当前技术的主要部分。本文提出了一种减少嵌入式系统数据缓存中泄漏能源消耗的技术，该技术基于以下事实：大多数存储的位的逻辑值为零。该技术已在当代高端嵌入式微处理器的模型上进行了评估，即ARM Cortex A8处理器，执行了一组标准嵌入式基准。实验结果表明，泄漏能源节省量约为40％，而没有IPC损失。
Nowadays, embedded systems can be found in a wide range of pervasive devices (e.g., smart phones, PDAs, or video/digital cameras). These devices contain large cache memories, whose power consumption can reach about 50% of the total spent energy, from which leakage energy is the predominant fraction in current technologies. This paper proposes a technique to reduce leakage energy consumption in data caches on embedded systems, which is based on the fact that most stored bits take a logical value of zero. The proposed technique has been evaluated on a model of a contemporary high-end embedded microprocessor, namely the ARM Cortex A8 processor, executing a set of standard embedded benchmarks. Experimental results show that leakage energy savings reach about 40% with no IPC loss.