DICE: Compressing DRAM caches for bandwidth and capacity
DICE: Compressing DRAM caches for bandwidth and capacity
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DOI：
10.1145/3079856.3080243
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发表时间：
2017-06
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通讯作者：
Vinson Young;Prashant J. Nair;Moinuddin K. Qureshi
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作者：
Vinson Young;Prashant J. Nair;Moinuddin K. Qureshi
本文研究DRAM高速缓存的压缩。由于DRAM高速缓存的容量通常很大，所以关于高速缓存压缩的现有技术（其仅关注于提高高速缓存容量）仅提供边际益处。我们表明，如果DRAM缓存的压缩量身定制，以提供更高的带宽，可以获得更多的性能优势。如果DRAM高速缓存可以在单次访问中提供两条压缩线，并且两条线都有用，则DRAM高速缓存的有效带宽将加倍。不幸的是，压缩DRAM缓存以获得带宽并不简单。通常使用的传统集合索引（TSI）将连续的线映射到连续的集合，因此从集合中获得的多个压缩线来自空间上遥远的位置，并且不太可能在彼此的短时间内使用。我们可以改变该高速缓存的索引，将连续的行放在同一个集合中以提高带宽;但是，当数据不可压缩时，这种空间索引会降低有效容量并导致显著的速度下降。理想情况下，我们希望在数据可压缩时使用空间索引，否则使用TSI。为此，我们提出了动态索引缓存压缩（DICE），一个动态的设计，可以适应空间索引和TSI之间，这取决于数据的可压缩性。我们还提出了低成本的高速缓存索引预测器（CIP），可以准确地预测该高速缓存索引方案的访问，以避免探测两个索引检索给定的高速缓存行。我们对1GB DRAM缓存的研究表明，在广泛的工作负载（包括SPEC和Graph）上，DICE平均将性能提高了19.0%，并将能量延迟积降低了36%。DICE是在3%的设计，有两倍的容量和两倍的带宽。DICE的存储开销小于1 KB，并且不依赖于任何操作系统支持。
This paper investigates compression for DRAM caches. As the capacity of DRAM cache is typically large, prior techniques on cache compression, which solely focus on improving cache capacity, provide only a marginal benefit. We show that more performance benefit can be obtained if the compression of the DRAM cache is tailored to provide higher bandwidth. If a DRAM cache can provide two compressed lines in a single access, and both lines are useful, the effective bandwidth of the DRAM cache would double. Unfortunately, it is not straight-forward to compress DRAM caches for bandwidth. The typically used Traditional Set Indexing (TSI) maps consecutive lines to consecutive sets, so the multiple compressed lines obtained from the set are from spatially distant locations and unlikely to be used within a short period of each other. We can change the indexing of the cache to place consecutive lines in the same set to improve bandwidth; however, when the data is incompressible, such spatial indexing reduces effective capacity and causes significant slowdown. Ideally, we would like to have spatial indexing when the data is compressible and TSI otherwise. To this end, we propose Dynamic-Indexing Cache comprEssion (DICE), a dynamic design that can adapt between spatial indexing and TSI, depending on the compressibility of the data. We also propose low-cost Cache Index Predictors (CIP) that can accurately predict the cache indexing scheme on access in order to avoid probing both indices for retrieving a given cache line. Our studies with a 1GB DRAM cache, on a wide range of workloads (including SPEC and Graph), show that DICE improves performance by 19.0% and reduces energy-delay-product by 36% on average. DICE is within 3% of a design that has double the capacity and double the bandwidth. DICE incurs a storage overhead of less than 1KB and does not rely on any OS support.