Challenges and design choices in nanoscale CMOS
Challenges and design choices in nanoscale CMOS
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纳米级 CMOS 的挑战和设计选择
DOI：
10.1145/1063803.1063805
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
S. Narendra
中科院分区：
文献类型：
--
作者：
S. Narendra
半导体行业增长的驱动力一直是CMOS技术的优雅缩放特性。在这篇文章中，我们将首先从微处理器设计的角度回顾遵循摩尔定律的技术规模的历史。挑战，继续历史的缩放趋势将突出和设计选择，以解决两个具体的挑战，工艺变化和泄漏功率，将进行讨论。在纳米级CMOS技术中，电源电压和阈值电压必须不断缩放，以保持性能提高、限制能耗、控制功耗并保持可靠性。这些对电源和阈值电压的持续缩放要求提出了若干技术和电路设计挑战。一个这样的挑战是工艺变化的预期增加以及由此导致的设计裕度的增加。将解释用于处理增加的设计裕度的自适应电路方案的概念。其次，随着阈值电压缩放，亚阈值泄漏功率已经成为纳米级CMOS系统中总功率的重要部分。因此，准确地预测和最小化这种系统的泄漏功率，特别是随着管芯内阈值电压变化的增加，变得势在必行。一个模型，预测系统泄漏的基础上的第一性原理和电路技术，以减少系统泄漏将进行讨论。需要指出的是，本文并没有涵盖纳米级CMOS系统面临的所有挑战。文章的主要部分中没有详细介绍的挑战和未来基于纳米硅的CMOS系统可能类似的猜测进行了总结。
The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In this article, we will first review the history of technology scaling that follows Moore's law from the prespective of microprocessor designs. Challenges to continue the historical scaling trends will be highlighted and design choices to address two specific challenges, process variation and leakage power, will be discussed. In nanoscale CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in process variation and the resulting increase in design margins. Concept of adaptive circuit schemes to deal with increasing design margins will be explained. Next, with threshold voltage scaling, subthreshold leakage power has become a significant portion of total power in nanoscale CMOS systems. Therefore, it has become imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and circuit techniques to reduce system leakage will be discussed. It is essential to point out that this article does not cover all challenges that nanoscale CMOS systems face. Challenges that are not detailed in the main sections of the article and speculation on what future nanoscale silicon based CMOS systems might resemble are summarized.