A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects
A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects
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基于与铜互连集成的 1T1MTJ 位单元的低功耗 1 Mbit MRAM
DOI：
10.1109/vlsic.2002.1015073
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
S. Tehrani
中科院分区：
文献类型：
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作者：
M. Durlam;Peter K. Naji;A. Omair;M. Deherrera;J. Calder;J. Slaughter;B. Engel;N. Rizzo;G. Grynkewich;B. Butcher;Clarence J. Tracy;K. Smith;K. Kyler;J. Ren;J. Molla;B. Feil;R. Williams;S. Tehrani
介绍了一种基于单晶体管和单磁性隧道结（1 T1 MTJ）位单元的低功耗1 Mb磁阻随机存取存储器（MRAM）。这是迄今为止最大的MRAM内存演示。在该电路中，MTJ元件使用铜互连技术与CMOS集成。铜互连件包覆有高导磁率层，所述高导磁率层用于将由流过线的电流产生的磁通量集中到MTJ装置且减少编程位所需的功率。25 mm/sup 2/ 1 Mb MRAM电路的地址访问时间小于50 ns，在3.0 V和20 MHz时功耗为24 mW。该电路是在0.6 /spl μ/m CMOS工艺，利用五层金属和两层多晶硅。
A low power 1 Mb Magnetoresistive Random Access Memory (MRAM) based on a 1-Transistor and 1-Magnetic Tunnel Junction (1T1MTJ) bit cell is demonstrated. This is the largest MRAM memory demonstration to date. In this circuit, MTJ elements are integrated with CMOS using copper interconnect technology. The copper interconnects are cladded with a high permeability layer which is used to focus magnetic flux generated by current flowing through the lines toward the MTJ devices and reduce the power needed for programming the bits. The 25 mm/sup 2/ 1 Mb MRAM circuit operates with address access times of less than 50 ns, consuming 24 mW at 3.0 V and 20 MHz. The circuit is fabricated in a 0.6 /spl mu/m CMOS process utilizing five layers of metal and two layers of poly.