Design of barrier bucket kicker control system-猫眼课题宝

障碍桶踢料器控制系统设计

DOI：

10.1016/j.nima.2018.02.086

发表时间：

2018-05

期刊：

Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

影响因子：

通讯作者：

中科院分区：

其他

文献类型：

作者：

Ni Fa Fu;Wang Yan Yu;Yin Jun;Zhou De Tai;Shen Guo Dong;Zhen Yang De;Zhang Jian Chuan;Yin Jia;Bai Xiao;Ma Xiao Li

兰州重离子加速器研究装置（HIRFL）包括两个同步加速器：主冷却储存环（CSRm）和实验冷却储存环（CSRe）。从CSRm中提取光束，并将其注入CSRe。为了将屏障桶（BB）方法应用于CSRe束流积累，设计并实现了一种基于BB技术的新型冲击器控制系统。该系统的控制器采用先进精简指令集计算机（RISC）机（ARM）芯片和现场可编程门阵列（FPGA）芯片实现。在该体系结构中，ARM负责数据预置和浮点运算处理。FPGA计算两个环的RF相位点，并提供更精确的时间延迟控制。在HIRFL上进行了在线初步实验，验证了控制系统的功能。结果表明，该方法可以获得任意相位点的两个不同正弦RF信号的参考触发点，相位误差小于1°（约2.1 ns），步进延迟时间优于2 ns。

The Heavy-Ion Research Facility in Lanzhou (HIRFL) contains two synchrotrons: the main cooler storage ring (CSRm) and the experimental cooler storage ring (CSRe). Beams are extracted from CSRm, and injected into CSRe. To apply the Barrier Bucket (BB) method on the CSRe beam accumulation, a new BB technology based kicker control system was designed and implemented. The controller of the system is implemented using an Advanced Reduced Instruction Set Computer (RISC) Machine (ARM) chip and a field-programmable gate array (FPGA) chip. Within the architecture, ARM is responsible for data presetting and floating number arithmetic processing. The FPGA computes the RF phase point of the two rings and offers more accurate control of the time delay. An online preliminary experiment on HIRFL was also designed to verify the functionalities of the control system. The result shows that the reference trigger point of two different sinusoidal RF signals for an arbitrary phase point was acquired with a matched phase error below 1° (approximately 2.1 ns), and the step delay time better than 2 ns were realized.