High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)
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DOI:
10.1109/tcpmt.2010.2101890
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发表时间:
2011-02-01
影响因子:
2.2
通讯作者:
Kim, Joungho
Kim, Joungho
中科院分区:
工程技术3区
文献类型:
--
作者:
Kim, Joohee;Pak, Jun So;Kim, Joungho

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提出了一种通硅通孔(TSV)的高频可扩展电学模型。该模型不仅包括TSV,还包括凸点和再分布层,它们是使用TSV进行3-D集成电路(IC)设计时的附加组件。所提出的模型是通过从物理构型推导出的解析方程建立的。每个解析式都是TSV、Bump和RDL设计参数的函数,因此是可伸缩的。通过三维场解算器对TSV直径、间距、高度等参数变化的模拟,验证了该模型的可扩展性。所提出的模型通过使用制造的TSV信道(包括TSV、BUPS和RDL)的测试车进行了高达20 GHz的测量来进行实验验证。基于所提出的可伸缩模型,我们在频域分析了TSV信道随设计参数变化时的电学行为。根据频域分析,在2 GHz以下,TSV的电容效应占主导地位。另一方面,当频率超过2 GHz时,RDLS的感应效应变得明显。通过眼图测量,在时间域中分析了电容型和阻型TSV信道的频变损耗。由于频率相关损耗,电压和时序裕度随着数据速率的增加而降低。
We propose a high-frequency scalable electrical model of a through silicon via (TSV). The proposed model includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3-D integrated circuit (IC) design. The proposed model is developed with analytic equations derived from the physical configuration. Each analytic equation is proposed as a function of design parameters of the TSV, bump, and RDL, and is therefore, scalable. The scalability of the proposed model is verified by simulation from the 3-D field solver with parameter variations, such as TSV diameter, pitch between TSVs, and TSV height. The proposed model is experimentally validated through measurements up to 20 GHz with fabricated test vehicles of a TSV channel, which includes TSVs, bumps, and RDLs. Based on the proposed scalable model, we analyze the electrical behaviors of a TSV channel with design parameter variations in the frequency domain. According to the frequency-domain analysis, the capacitive effect of a TSV is dominant under 2 GHz. On the other hand, as frequency increases over 2 GHz, the inductive effect from the RDLs becomes significant. The frequency dependent loss of a TSV channel, which is capacitive and resistive, is also analyzed in the time domain by eye-diagram measurements. Due to the frequency dependent loss, the voltage and timing margins decrease as the data rate increases.