A 1.2V, 140GHz receiver with on-die antenna in 65nm CMOS
A 1.2V, 140GHz receiver with on-die antenna in 65nm CMOS
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DOI：
10.1109/rfic.2008.4561424
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发表时间：
2008-07
期刊：
影响因子：
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通讯作者：
S. Nicolson;A. Tomkins;K. W. Tang;A. Cathelin;D. Belot;S. Voinigescu
中科院分区：
文献类型：
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作者：
S. Nicolson;A. Tomkins;K. W. Tang;A. Cathelin;D. Belot;S. Voinigescu
本文介绍了一种1.2V、100 mW、140 GHz的接收器，该接收器具有片上天线，采用65 nm通用(GP)工艺，具有数字后端。该接收机在100-140 GHz范围内具有15-19分贝的转换损耗和102 GHz的LO，芯片面积仅为580微米乘以700微米(包括焊盘)。该低噪声放大器在140 GHz、10 GHz带宽下实现了8dBm的增益，饱和输出功率至少为-1.8dBm，在125℃时保持了3dBm的增益。该片上天线满足65 nm CMOS片内密度填充要求，增益为-25d B，芯片面积为180um×100um。此外，还讨论了使CMOS器件的毫米波性能最大化的设计技术。
This paper presents a 1.2 V, 100 mW, 140 GHz receiver with on-die antenna in a 65 nm General Purpose (GP) CMOS process with digital back-end. The receiver has a conversion loss of 15-19 dB in the 100-140 GHz range with 102 GHz LO, and occupies a die area of only 580 mum times 700 mum including pads. The LNA achieves 8 dB gain at 140 GHz, 10 GHz bandwidth, at least -1.8 dBm of saturated output power, and maintains 3 dB gain at 125 degC. The on-chip antenna, which meets all density fill requirements of 65 nm CMOS, has -25 dB gain, and occupies 180 mum times 100 mum of die area. Additionally, design techniques which maximize the millimeter-wave performance of CMOS devices are discussed.