Silicon single electron transistors fabricated by chemical mechanical polishing
Silicon single electron transistors fabricated by chemical mechanical polishing
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化学机械抛光制备硅单电子晶体管
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发表时间：
2010
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通讯作者：
Yen
中科院分区：
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作者：
Yen
作者报告了一种新型单电子晶体管（SET）制造技术的结果，该技术结合了化学机械抛光的独特优势以及硅加工的多功能性和可扩展性。通过纳米封装将绝缘体上简并掺杂硅的薄（约15 nm）线嵌入平坦化的等离子体增强化学气相沉积氧化物中。这条线中的坑是通过高选择性硅干法蚀刻形成的，并且使用快速热氧化在坑的侧壁上生长隧道氧化物。简并掺杂的非晶硅被沉积到坑中以形成SET岛，硅的覆盖层被去除，并且结构通过化学机械抛光减薄。SET的充电图表明充电能量约为20 meV，这归功于其小的隧道结尺寸以及岛和引线内掺杂剂分布可能形成的“熔池”。观察到的异常，如丢失和分裂的钻石在充电情节和随机电报信号，表明供体网站在设备的操作中发挥了重要作用。几个制造的SET显示出类似的库仑阻塞在4 K，表现出合理的产量的process.The作者报告的结果，一种新的单电子晶体管（SET）的制造技术，结合了独特的优势，化学机械抛光和硅加工的多功能性和可扩展性。通过纳米封装将绝缘体上简并掺杂硅的薄（约15 nm）线嵌入平坦化的等离子体增强化学气相沉积氧化物中。这条线中的坑是通过高选择性硅干法蚀刻形成的，并且使用快速热氧化在坑的侧壁上生长隧道氧化物。简并掺杂的非晶硅被沉积到坑中以形成SET岛，硅的覆盖层被去除，并且结构通过化学机械抛光减薄。SET的充电图表明充电能量约为20 meV，这归功于其小的隧道结尺寸以及岛和引线内掺杂剂分布可能形成的“熔池”。观察到的异常，如失踪和分裂的钻石是一个...
The authors report the results of a novel single electron transistor (SET) fabrication technique that combines the unique advantages of chemical mechanical polishing and the versatility and scalability of silicon processing. A thin (∼15 nm) line of degenerately doped silicon on insulator is embedded in a planarized plasma enhanced chemical vapor deposition oxide through nanoencapsulation. A pit in this line is formed by a highly selective silicon dry etch, and the tunnel oxide is grown on the sidewalls of the pit using rapid thermal oxidation. Degenerately doped amorphous silicon is deposited into the pit to form the SET island, the overburden of silicon is removed, and the structure is thinned down by chemical mechanical polishing. The SET’s charging diagram indicates a charging energy of around 20 meV, credited to its small tunnel junction size as well as possible “puddle” formation from the dopant distribution within the island and the leads. The observed anomalies, such as missing and split diamonds in the charging plots and random telegraph signals, suggest that the donor sites play an important role in the device operation. Several fabricated SETs show a similar Coulomb blockade at 4 K, demonstrating reasonable yield for the process.The authors report the results of a novel single electron transistor (SET) fabrication technique that combines the unique advantages of chemical mechanical polishing and the versatility and scalability of silicon processing. A thin (∼15 nm) line of degenerately doped silicon on insulator is embedded in a planarized plasma enhanced chemical vapor deposition oxide through nanoencapsulation. A pit in this line is formed by a highly selective silicon dry etch, and the tunnel oxide is grown on the sidewalls of the pit using rapid thermal oxidation. Degenerately doped amorphous silicon is deposited into the pit to form the SET island, the overburden of silicon is removed, and the structure is thinned down by chemical mechanical polishing. The SET’s charging diagram indicates a charging energy of around 20 meV, credited to its small tunnel junction size as well as possible “puddle” formation from the dopant distribution within the island and the leads. The observed anomalies, such as missing and split diamonds i...