Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic
Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic
复制标题
基于多值多路复用器逻辑的细粒度流水线可重构VLSI架构
DOI：
10.1109/ismvl.2017.45
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发表时间：
2017
期刊：
影响因子：
--
通讯作者：
M. Kameyama
中科院分区：
文献类型：
--
作者：
Katsuhiko Shimabukuro;M. Kameyama
提出了一种新的基于多路复用逻辑的位串行细粒度流水线可重构VLSI结构，以实现高硬件资源利用率和高吞吐量。基本单元由一个2路数据输入的多路复用器和一个开关盒组成的逻辑块构成，相邻逻辑块之间通过8邻域网状网络进行数据传输。一个多路复用器合并一个锁存功能，有效地采用高效的细粒度流水线操作。提出了一种基于数据流图的流水线位串行操作的系统映射方法。作为基于二进制多路复用逻辑的可重构VLSI的扩展，我们在逻辑块之间的数据传输中引入了线性求和。可有效地利用由线性和直接控制的4值多路复用器来降低开关盒的复杂性。
This paper presents a novel bit-serial fine-grain pipelined reconfigurable VLSI architecture based on multiplexer logic to achieve high utilization of hardware resources and high throughput. A basic cell is constructed by a logic block composed of a 2-data-input multiplexer and a switch box for data transfer between adjacent logic blocks by 8-near neighborhood mesh network. A multiplexer merged with a latch function is effectively employed for efficient fine-grain pipelined operation. A systematic mapping method for pipelined bit-serial operations is proposed using a data flow graph. As an extension of the reconfigurable VLSI based on the binary multiplexer logic, we introduce linear summation in the data transfer between logic blocks. A 4-valued multiplexer directly controlled by the linear sum can be effectively utilized to reduce complexity of the switch box.
基于多值X-Net数据传输方案的位串行可重构VLSI
影响因子：
0.7
作者：
Xu Bai;Michitaka Kameyama
通讯作者：
Michitaka Kameyama